An AI-based approach to Noise Reduction in Electronic Circuits

A channel is a rectangular region of VLSI layout, between pair of adjacent blocks and is used for interconnecting the nets of signal, clock, and ground. With increased scaling of the chips, the coupling capacitance between the interconnect lines becomes predominant. This capacitance along with the increased interconnect lengths, clock frequencies and reduced supply voltages lead to noise in nets. A high-performance channel router needs to minimize noise. We apply the A* algorithm for a channel router to find a minimum-track solution with minimum noise. Empirically, the proposed algorithm yields an average of 37.5% noise reduction over a standard minimum-track routing solution, which is highly encouraging.